ADZS-BF527-EZLITE【PDF 15/88 页】BOARD EVAL ADSP-BF527

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

System DMA access to L1 memory is not supported in

sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but cannot access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in deep

sleep mode, an RTC asynchronous interrupt causes the proces-

sor to transition to the Active mode. Assertion of RESET while

in deep sleep mode causes the processor to transition to the full

Power Savings

As shown in Table 5 , the processor supports six different power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions. By isolating

the internal logic of the processor into its own power domain,

separate from the RTC and other I/O, the processor can take

advantage of dynamic power management without affecting the

RTC or other I/O devices. There are no sequencing require-

ments for the various power domains, but all domains must be

powered according to the appropriate Specifications table for

processor Operating Conditions; even if the feature/peripheral

is not used.

Table 5. Power Domains

on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the synchronous peripherals (SCLK). The internal voltage regu-

lator (ADSP-BF523/ADSP-BF525/ADSP-BF527 only) for the

processor can be shut off by writing b#00 to the FREQ bits of the

VR_CTL register, using the bfrom_SysControl() function. This

Power Domain

All internal logic, except RTC, Memory, USB, OTP

RTC internal logic and crystal I/O

Memory logic

USB PHY logic

OTP logic

All other I/O

V DD Range

V DDINT

V DDRTC

V DDMEM

V DDUSB

V DDOTP

V DDEXT

= -------------------------- ? ? -------------------------------- ? ? ? --------------- ?

setting sets the internal power supply voltage (V DDINT ) to 0 V to

provide the lowest static power dissipation. Any critical infor-

mation stored internally (for example, memory contents,

register contents, and other information) must be written to a

non volatile storage device prior to removing power if the pro-

cessor state is to be preserved. Writing b#00 to the FREQ bits

also causes EXT_WAKE0 and EXT_WAKE1 to transition low,

which can be used to signal an external voltage regulator to

shut down.

Since V DDEXT and V DDMEM can still be supplied in this mode, all

of the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

still have power applied without drawing unwanted current.

The Ethernet or USB modules can wake up the internal supply

regulator (ADSP-BF525 and ADSP-BF527 only) or signal an

external regulator to wake up using EXT_WAKE0 or

EXT_WAKE1. If PG15 does not connect as a PHYINT signal to

an external PHY device, PG15 can be pulled low by any other

device to wake the processor up. The processor can also be

woken up by a real-time clock wakeup event or by asserting the

RESET pin. All hibernate wake-up events initiate the hardware

reset sequence. Individual sources are enabled by the VR_CTL

register. The EXT_WAKEx signals are provided to indicate the

occurrence of wake-up events.

As long as V DDEXT is applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state. State

variables may be held in external SRAM or SDRAM. The

SCKELOW bit in the VR_CTL register controls whether or not

SDRAM operates in self-refresh mode, which allows it to retain

its content while the processor is in hibernate and through the

subsequent reset sequence.

The dynamic power management feature of the processor

allows both the processor’s input voltage (V DDINT ) and clock fre-

quency (f CCLK ) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Power Savings Factor

f CCLKRED V DDINTRED 2 T RED

f CCLKNOM ? V DDINTNOM ? ? T NOM ?

% Power Savings = ? 1 – Power Savings Factor ? ? 100%

where the variables in the equations are:

f CCLKNOM is the nominal core clock frequency

f CCLKRED is the reduced core clock frequency

V DDINTNOM is the nominal internal supply voltage

V DDINTRED is the reduced internal supply voltage

T NOM is the duration running at f CCLKNOM

T RED is the duration running at f CCLKRED

Rev. D |

Page 15 of 88 | July 2013

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